Download or read book Architectural Support for Efficient Virtual Memory on Big memory Systems written by Binh Quang Pham and published by . This book was released on 2016 with total page 116 pages. Available in PDF, EPUB and Kindle. Book excerpt: Virtual memory is a powerful and ubiquitous abstraction for managing memory. How- ever, virtual memory suffers a performance penalty for these benefits, namely when translating program virtual addresses to system physical addresses. This overhead had been limited to 5-15% of system runtime by using a set of sophisticated hardware so- lutions, but has increased to 20-50% for many scenarios, including running workloads with large memory footprints and poor access locality or using deeper software stacks. My thesis aims to solve this problem so that the memory systems can continue to scale without being hamstrung by the virtual memory system. We observe that while operating systems (OS) and hypervisors have a rich set of components in allocating memory, the hardware address translation unit only maintains a rigid and limited view of this ecosystem. Therefore, we seek for patterns inherently present in the memory allocation mechanisms to guide us in designing a more intelligent address translation unit. First, we realize that OS memory allocators and program faulting sequence tend to produce contiguous or nearby mappings between virtual and physical pages. We propose Coalesced TLB and Clustered TLB designs to exploit these patterns accordingly. Once detected, the related mappings are stored in a single TLB entry to increase the TLB's reach. Our designs help reduce TLB misses substantially and improve performance as a result. Second, we see that there are often tradeoffs between reducing address translation overheard and improving resource consolidation in virtualized environments. For exam- ple, large pages are often used to mitigate the high cost of two-dimensional page walks, but hypervisors usually break large pages into small pages for easier sharing guests memory. When that happens, the majority of those small pages still remain aligned. Based on this observation, we propose a speculative TLB technique to regain almost all performance loss caused by breaking large pages while running highly consolidated virtualized systems.

Download or read book Architectural and Operating System Support for Virtual Memory written by Abhishek Bhattacharjee and published by Springer. This book was released on 2017-09-29 with total page 157 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book provides computer engineers, academic researchers, new graduate students, and seasoned practitioners an end-to-end overview of virtual memory. We begin with a recap of foundational concepts and discuss not only state-of-the-art virtual memory hardware and software support available today, but also emerging research trends in this space. The span of topics covers processor microarchitecture, memory systems, operating system design, and memory allocation. We show how efficient virtual memory implementations hinge on careful hardware and software cooperation, and we discuss new research directions aimed at addressing emerging problems in this space. Virtual memory is a classic computer science abstraction and one of the pillars of the computing revolution. It has long enabled hardware flexibility, software portability, and overall better security, to name just a few of its powerful benefits. Nearly all user-level programs today take for granted that they will have been freed from the burden of physical memory management by the hardware, the operating system, device drivers, and system libraries. However, despite its ubiquity in systems ranging from warehouse-scale datacenters to embedded Internet of Things (IoT) devices, the overheads of virtual memory are becoming a critical performance bottleneck today. Virtual memory architectures designed for individual CPUs or even individual cores are in many cases struggling to scale up and scale out to today's systems which now increasingly include exotic hardware accelerators (such as GPUs, FPGAs, or DSPs) and emerging memory technologies (such as non-volatile memory), and which run increasingly intensive workloads (such as virtualized and/or "big data" applications). As such, many of the fundamental abstractions and implementation approaches for virtual memory are being augmented, extended, or entirely rebuilt in order to ensure that virtual memory remains viable and performant in the years to come.

Download or read book High Performance Memory Systems written by Haldun Hadimioglu and published by Springer Science & Business Media. This book was released on 2011-06-27 with total page 298 pages. Available in PDF, EPUB and Kindle. Book excerpt: The State of Memory Technology Over the past decade there has been rapid growth in the speed of micropro cessors. CPU speeds are approximately doubling every eighteen months, while main memory speed doubles about every ten years. The International Tech nology Roadmap for Semiconductors (ITRS) study suggests that memory will remain on its current growth path. The ITRS short-and long-term targets indicate continued scaling improvements at about the current rate by 2016. This translates to bit densities increasing at two times every two years until the introduction of 8 gigabit dynamic random access memory (DRAM) chips, after which densities will increase four times every five years. A similar growth pattern is forecast for other high-density chip areas and high-performance logic (e.g., microprocessors and application specific inte grated circuits (ASICs)). In the future, molecular devices, 64 gigabit DRAMs and 28 GHz clock signals are targeted. Although densities continue to grow, we still do not see significant advances that will improve memory speed. These trends have created a problem that has been labeled the Memory Wall or Memory Gap.

Download or read book The Memory System written by Bruce Jacob and published by Morgan & Claypool Publishers. This book was released on 2009-07-08 with total page 77 pages. Available in PDF, EPUB and Kindle. Book excerpt: Today, computer-system optimization, at both the hardware and software levels, must consider the details of the memory system in its analysis; failing to do so yields systems that are increasingly inefficient as those systems become more complex. This lecture seeks to introduce the reader to the most important details of the memory system; it targets both computer scientists and computer engineers in industry and in academia. Roughly speaking, computer scientists are the users of the memory system and computer engineers are the designers of the memory system. Both can benefit tremendously from a basic understanding of how the memory system really works: the computer scientist will be better equipped to create algorithms that perform well and the computer engineer will be better equipped to design systems that approach the optimal, given the resource limitations. Currently, there is consensus among architecture researchers that the memory system is "the bottleneck," and this consensus has held for over a decade. Somewhat inexplicably, most of the research in the field is still directed toward improving the CPU to better tolerate a slow memory system, as opposed to addressing the weaknesses of the memory system directly. This lecture should get the bulk of the computer science and computer engineering population up the steep part of the learning curve. Not every CS/CE researcher/developer needs to do work in the memory system, but, just as a carpenter can do his job more efficiently if he knows a little of architecture, and an architect can do his job more efficiently if he knows a little of carpentry, giving the CS/CE worlds better intuition about the memory system should help them build better systems, both software and hardware. Table of Contents: Primers / It Must Be Modeled Accurately / ...\ and It Will Change Soon

Download or read book Architectural and Operating System Support for Virtual Memory written by Abhishek Bhattacharjee and published by Springer Nature. This book was released on 2022-05-31 with total page 168 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book provides computer engineers, academic researchers, new graduate students, and seasoned practitioners an end-to-end overview of virtual memory. We begin with a recap of foundational concepts and discuss not only state-of-the-art virtual memory hardware and software support available today, but also emerging research trends in this space. The span of topics covers processor microarchitecture, memory systems, operating system design, and memory allocation. We show how efficient virtual memory implementations hinge on careful hardware and software cooperation, and we discuss new research directions aimed at addressing emerging problems in this space. Virtual memory is a classic computer science abstraction and one of the pillars of the computing revolution. It has long enabled hardware flexibility, software portability, and overall better security, to name just a few of its powerful benefits. Nearly all user-level programs today take for granted that they will have been freed from the burden of physical memory management by the hardware, the operating system, device drivers, and system libraries. However, despite its ubiquity in systems ranging from warehouse-scale datacenters to embedded Internet of Things (IoT) devices, the overheads of virtual memory are becoming a critical performance bottleneck today. Virtual memory architectures designed for individual CPUs or even individual cores are in many cases struggling to scale up and scale out to today's systems which now increasingly include exotic hardware accelerators (such as GPUs, FPGAs, or DSPs) and emerging memory technologies (such as non-volatile memory), and which run increasingly intensive workloads (such as virtualized and/or "big data" applications). As such, many of the fundamental abstractions and implementation approaches for virtual memory are being augmented, extended, or entirely rebuilt in order to ensure that virtual memory remains viable and performant in the years to come.

Download or read book Performance Improvement of Virtual Memory Systems written by Edwin James Lau and published by . This book was released on 1982 with total page 240 pages. Available in PDF, EPUB and Kindle. Book excerpt:

Download or read book Efficient Fine grained Virtual Memory written by Tianhao Zheng (Ph. D.) and published by . This book was released on 2018 with total page 252 pages. Available in PDF, EPUB and Kindle. Book excerpt: Virtual memory in modern computer systems provides a single abstraction of the memory hierarchy. By hiding fragmentation and overlays of physical memory, virtual memory frees applications from managing physical memory and improves programmability. However, virtual memory often introduces noticeable overhead. State-of-the-art systems use a paged virtual memory that maps virtual addresses to physical addresses in page granularity (typically 4 KiB ).This mapping is stored as a page table. Before accessing physically addressed memory, the page table is accessed to translate virtual addresses to physical addresses. Research shows that the overhead of accessing the page table can even exceed the execution time for some important applications. In addition, this fine-grained mapping changes the access patterns between virtual and physical address spaces, introducing difficulties to many architecture techniques, such as caches and prefecthers. In this dissertation, I propose architecture mechanisms to reduce the overhead of accessing and managing fine-grained virtual memory without compromising existing benefits. There are three main contributions in this dissertation. First, I investigate the impact of address translation on cache. I examine the restriction of virtually indexed, physically tagged (VIPT) caches with fine-grained paging and conclude that this restriction may lead to sub-optimal cache designs. I introduce a novel cache strategy, speculatively indexed, physically tagged (SIPT) to enable flexible cache indexing under fine-grained page mapping. SIPT speculates on the value of a few more index bits (1 - 3 in our experiments) to access the cache speculatively before translation, and then verify that the physical tag matches after translation. Utilizing the fact that a simple relation generally exists between virtual and physical addresses, because memory allocators often exhibit contiguity, I also propose low-cost mechanisms to predict and correct potential mis-speculations. Next, I focus on reducing the overhead of address translation for fine-grained virtual memory. I propose a novel architecture mechanism, Embedded Page Translation Information (EMPTI), to provide general fine-grained page translation information on top of coarse-grained virtual memory. EMPTI does so by speculating that a virtual address is mapped to a pre-determined physical location and then verifying the translation with a very-low-cost access to metadata embedded with data. Coarse-grained virtual memory mechanisms (e.g., segmentation) are used to suggest the pre-determined physical location for each virtual page. Overall, EMPTI achieves the benefits of low overhead translation while keeping the flexibility and programmability of fine-grained paging. Finally, I improve the efficiency of metadata caching based on the fact that memory mapping contiguity generally exists beyond a page boundary. In state-of-the-art architectures, caches treat PTEs (page table entries) as regular data. Although this is simple and straightforward, it fails to maximize the storage efficiency of metadata. Each page in the contiguously mapped region costs a full 8-byte PTE. However, the delta between virtual addresses and physical addresses remain the same and most metadata are identical. I propose a novel microarchitectural mechanism that expands the effective PTE storage in the last-level-cache (LLC) and reduces the number of page-walk accesses that miss the LLC.

Download or read book Improving the Performance and Energy efficiency of Virtual Memory written by Vasileios Karakostas and published by . This book was released on 2016 with total page 173 pages. Available in PDF, EPUB and Kindle. Book excerpt: Virtual memory improves programmer productivity, enhances process security, and increases memory utilization. However, virtual memory requires an address translation from the virtual to the physical address space on every memory operation. Page-based implementations of virtual memory divide physical memory into fixed size pages, and use a per-process page table to map virtual pages to physical pages. The hardware key component for accelerating address translation is the Translation Lookaside Buffer (TLB), that holds recently used mappings from the virtual to the physical address space. However, address translation still incurs high (i) performance overheads due to costly page table walks after TLB misses, and (ii) energy overheads due to frequent TLB lookups on every memory operation. This thesis quantifies these overheads and proposes techniques to mitigate them. In this thesis we argue that fixed size page-based approaches for address translation exhibit limited potential for improving TLB performance because they increase the TLB reach by a fixed amount. To overcome the limitations of such approaches, we introduce the concept of range translations and we show how they can significantly improve the performance and energy-efficiency of address translation. We first comprehensively quantify the address translation performance overhead on a collection of emerging scale-out applications. We show that address translation accounts for up to 16% of the total execution time. We find that huge pages may improve the application performance by reducing the time spent in page walks, enabling better exploitation of the available execution resources. However, the limited hardware support for huge pages in combination with the workloads' low memory locality leave ample space for performance optimizations. To reduce the performance overheads of address translation, we propose Redundant Memory Mappings (R10). R10 provides an efficient alternative representation of many virtual-to-physical mappings. We define a range translation be a subset of a process's pages that are virtually and physically contiguous. R10 translates each range translation with a single range table entry, enabling a modest number of entries to translate most of the process's address space. R10 operates in parallel with standard paging and introduces a software range table and a hardware range TLB with arbitrarily large reach that is accessed in parallel with the regular L2-page TLB. We modify the operating system to automatically detect ranges and to increase their likelihood with eager paging. R10 is thus transparent to applications. We prototype R10 software in Linux and emulate the hardware. R10 reduces the overhead of virtual memory to less than 1% on average on a wide range of workloads. To reduce the energy cost of address translation, we propose the Lite mechanism and the TLB-Lite and R10-Lite designs. Lite monitors the performance and utility of L1 TLBs, and adaptively changes their sizes with way-disabling. The resulting TLB-Lite design targets commodity processors with TLB support for huge pages and opportunistically reduces the dynamic energy spent in address translation with minimal impact on TLB miss cycles. To further provide more energy-efficient address translation, we propose R10-Lite that adds to R10 an L1-range TLB, that is accessed in parallel with the regular L1-page TLB, and the Lite mechanism. The high hit ratio of the L1-range TLB allows Lite to downsize the L1-page TLBs more aggressively. R10-Lite reduces the dynamic energy spent in address translation by 71% on average. Above the near-zero L2 TLB misses from R10, R10-Lite further reduces the overhead from L1 TLB misses by 99\%. The proposed designs target current and future high-performance and energy-efficient memory systems to meet the ever increasing memory demands of applications.

Download or read book Memory Architecture Exploration for Programmable Embedded Systems written by Peter Grun and published by Springer Science & Business Media. This book was released on 2003 with total page 139 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book presents a "compiler-in-the-loop" exploration strategy for alternative memory architectures, allowing for effective matching of the target application to the processor-memory architecture. This new approach for memory architecture exploration replaces the traditional black-box view of the memory system. The utility of the approach is illustrated for a set of large, real-life benchmarks. Material is of interest to different groups in the embedded systems-on-chip field, including researchers and students in memory architecture, CAD developers, and system designers. Grun is affiliated with the Center for Embedded Computer Systems, University of California-Irvine. Annotation (c)2003 Book News, Inc., Portland, OR (booknews.com).

Download or read book Performance Improvement of Virtual Memory Systems by Restructuring and Prefetching written by Edwin James Lau and published by . This book was released on 1979 with total page 658 pages. Available in PDF, EPUB and Kindle. Book excerpt:

Download or read book Innovations in the Memory System written by Rajeev Balasubramonian and published by Morgan & Claypool Publishers. This book was released on 2019-09-10 with total page 153 pages. Available in PDF, EPUB and Kindle. Book excerpt: This is a tour through recent and prominent works regarding new DRAM chip designs and technologies, near data processing approaches, new memory channel architectures, techniques to tolerate the overheads of refresh and fault tolerance, security attacks and mitigations, and memory scheduling. The memory system will soon be a hub for future innovation. While conventional memory systems focused primarily on high density, other memory system metrics like energy, security, and reliability are grabbing modern research headlines. With processor performance stagnating, it is also time to consider new programming models that move some application computations into the memory system. This, in turn, will lead to feature-rich memory systems with new interfaces. The past decade has seen a number of memory system innovations that point to this future where the memory system will be much more than dense rows of unintelligent bits.

Download or read book Structuring Programs for Efficient Operation in Virtual Memory Systems written by Anthony L. Barrese and published by . This book was released on 1977 with total page 0 pages. Available in PDF, EPUB and Kindle. Book excerpt:

Download or read book A Class of Real time Virtual Memory Systems written by Philip Avery Johnson and published by . This book was released on 1973 with total page 400 pages. Available in PDF, EPUB and Kindle. Book excerpt:

Download or read book The Architecture of the Oasis Mobile Shared Virtual Memory System written by William Harold Schroeder and published by . This book was released on 1996 with total page 380 pages. Available in PDF, EPUB and Kindle. Book excerpt:

Download or read book Virtual Memory Management written by Richard William Carr and published by . This book was released on 1981 with total page 262 pages. Available in PDF, EPUB and Kindle. Book excerpt:

Download or read book Architectural Support for Persistent Memory Systems written by Arpit Jayendrakumar Joshi and published by . This book was released on 2018 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt:

Download or read book Architectural Support for Cache coherent Active Memory Systems written by Daehyun Kim and published by . This book was released on 2003 with total page 456 pages. Available in PDF, EPUB and Kindle. Book excerpt: