Download or read book A Study of the Gate Engineering of the Ge MOS Capacitor and N MOSFET Devices Using ZrO2 as Gate Dielectric written by and published by . This book was released on 2017 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt:

Download or read book Interface engineered Ge MOSFETs for Future High Performance CMOS Applications written by Duygu Kuzum and published by Stanford University. This book was released on 2009 with total page 159 pages. Available in PDF, EPUB and Kindle. Book excerpt: As the semiconductor industry approaches the limits of traditional silicon CMOS scaling, introduction of performance boosters like novel materials and innovative device structures has become necessary for the future of CMOS. High mobility materials are being considered to replace Si in the channel to achieve higher drive currents and switching speeds. Ge has particularly become of great interest as a channel material, owing to its high bulk hole and electron mobilities. However, replacement of Si channel by Ge requires several critical issues to be addressed in Ge MOS technology. High quality gate dielectric for surface passivation, low parasitic source/drain resistance and performance improvement in Ge NMOS are among the major challenges in realizing Ge CMOS. Detailed characterization of gate dielectric/channel interface and a deeper understanding of mobility degradation mechanisms are needed to address the Ge NMOS performance problem and to improve PMOS performance. In the first part of this dissertation, the electrical characterization results on Ge NMOS and PMOS devices fabricated with GeON gate dielectric are presented. Carrier scattering mechanisms are studied through low temperature mobility measurements. For the first time, the effect of substrate crystallographic orientation on inversion electron and hole mobilities is investigated. Direct formation of a high-k dielectric on Ge has not given good results in the past. A good quality interface layer is required before the deposition of a high-K dielectric. In the second part of this dissertation, ozone-oxidation process is introduced to engineer Ge/insulator interface. Electrical and structural characterizations and stability analysis are carried out and high quality Ge/dielectric interface with low interface trap density is demonstrated. Detailed extraction of interface trap density distribution across the bandgap and close to band edges of Ge, using low temperature conductance and capacitance measurements is presented. Ge N-MOSFETs have exhibited poor drive currents and low mobility, as reported by several different research groups worldwide. In spite of the increasing interest in Ge, the major mechanisms behind poor Ge NMOS performance have not been completely understood yet. In the last part of this dissertation, the results on Ge NMOS devices fabricated with the ozone-oxidation and the low temperature source/drain activation processes are discussed. These devices achieve the highest electron mobility to-date, about 1.5 times the universal Si mobility. Detailed interface characterizations, trapping analyses and gated Hall device measurements are performed to identify the mechanisms behind poor Ge NMOS performance in the past.

Download or read book Gate Dielectrics and MOS ULSIs written by Takashi Hori and published by Springer Science & Business Media. This book was released on 2012-12-06 with total page 362 pages. Available in PDF, EPUB and Kindle. Book excerpt: Gate Dielectrics and MOS ULSIs provides necessary and sufficient information for those who wish to know well and go beyond the conventional SiO2 gate dielectric. The topics particularly focus on dielectric films satisfying the superior quality needed for gate dielectrics even in large-scale integration. And since the quality requirements are rather different between device applications, they are selected in an applicatipn-oriented manner, e.g., conventional SiO2 used in CMOS logic circuits, nitrided oxides, which recently became indispensable for flash memories, and composite ONO and ferroelectric films for passive capacitors used in DRAM applications. The book also covers issues common to all gate dielectrics, such as MOSFET physics, evaluation, scaling, and device application/integration for successful development. The information is as up to date as possible, especially for nanometer-range ultrathin gate-dielectric films indispensible in submicrometer ULSIs. The text together with abundant illustrations will take even the inexperienced reader up to the present high state of the art. It is the first book presenting nitrided gate oxides in detail.

Download or read book Physics and Technology of High k Gate Dielectrics 6 written by S. Kar and published by The Electrochemical Society. This book was released on 2008-10 with total page 550 pages. Available in PDF, EPUB and Kindle. Book excerpt: The issue covers in detail all aspects of the physics and the technology of high dielectric constant gate stacks, including high mobility substrates, novel and still higher permittivity dielectric materials, CMOS processing with high-K layers, metals for gate electrodes, interface issues, physical, chemical, and electrical characterization, gate stack reliability, and DRAM and non-volatile memories.

Download or read book A Study on Gate Dielectrics for GE Mos Devices written by Chunxia Li and published by Open Dissertation Press. This book was released on 2017-01-28 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt: This dissertation, "A Study on Gate Dielectrics for Ge MOS Devices" by Chunxia, Li, 李春霞, was obtained from The University of Hong Kong (Pokfulam, Hong Kong) and is being sold pursuant to Creative Commons: Attribution 3.0 Hong Kong License. The content of this dissertation has not been altered in any way. We have altered the formatting in order to facilitate the ease of printing and reading of the dissertation. All rights not granted by the above license are retained by the author. DOI: 10.5353/th_b4370387 Subjects: Dielectrics Metal oxide semiconductors, Complementary Germanium

Download or read book Advanced Gate Stacks for High Mobility Semiconductors written by Athanasios Dimoulas and published by Springer Science & Business Media. This book was released on 2008-01-01 with total page 397 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book provides a comprehensive monograph on gate stacks in semiconductor technology. It covers the major latest developments and basics and will be useful as a reference work for researchers, engineers and graduate students alike. The reader will get a clear view of what has been done so far, what is the state-of-the-art and which are the main challenges ahead before we come any closer to a viable Ge and III-V MOS technology.

Download or read book Gate Stack and Channel Engineering written by Ravi M. Todi and published by . This book was released on 2007 with total page 136 pages. Available in PDF, EPUB and Kindle. Book excerpt: The continued scaling of device dimensions in complementary metal oxide semiconductor (CMOS) technology within the sub-100 nm region requires an alternative high dielectric constant (high-k) oxide layer to counter high tunneling leakage currents, a metallic gate electrode to address polysilicon depletion, boron penetration and high polysilicon sheet resistance, and high mobility channel materials to boost the CMOS performance. Metal gates can also offer improved thermal and chemical stability, but their use requires we improve our understanding of the how the metal alloy phase, crystallographic orientation, and composition affect the electronic properties of the metal alloy-oxide interface. To replace n++ and p ++ polysilicon gate electrodes and maintain scaled device performance requires metal gate electrodes with work functions within 0.2 eV of the silicon conduction and valence band edges, i.e., 5.0-5.2 and 4.1-4.3 eV, for PMOS and NMOS devices, respectively. In addition to work function and thermal/chemical stability, metal gates must be integrated into the CMOS process flow. It is the aim of this work to significantly expand our knowledge base in alloys for dual metal gates by carrying out detailed electrical and materials studies of the binary alloy systems of Ru with p-type metal Pt. Three n-type metals systems, Ru-Ta, Ru-Hf and Ru-Nb have also been partially investigated. This work also focuses on high mobility Ge p-MOSFETs for improved CMOS performance. DC magnetron sputtering has been used to deposity binary alloy films on thermally gorwn SiO2. The composition of the alloy films have been determined by Rutherford backscattering spectrometry and the identification of phases present have been made using x-ray and electron diffraction of samples. The microstructure of the phases of interest has been examined in the transmission electron microscope and film texture was characterized via x-ray diffraction. The electrical characterization includes basic resistivity measurements, and work function extraction. The work function has been determined from MOS capacitor and Schottky diodes. The need for electron and hole mobility enhancement and the progress in the development of high-k gate stacks, has lead to renewed interest in Ge MOSFETs. The p-MOS mobility data for Ge channel devices have been reported. The results indicate greater than 2 x improvements in device mobility as compared to standard Si device. A low frequency noise assessment of silicon passivated Ge p-MOSFETs with a TiN/TaN/HfO2 gate stack has been made. For the first time we also report results on low frequency noicse characterisation for a Ge P-n junctions with and without Ni germanidation.

Download or read book Process Study of Higher k Gate Dielectric and Si Ge Channel in MOS Devices written by 傅崇豪 and published by . This book was released on 2014 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt:

Download or read book The Source Drain Engineering of Nanoscale Germanium based MOS Devices written by Zhiqiang Li and published by Springer. This book was released on 2016-03-24 with total page 71 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book mainly focuses on reducing the high parasitic resistance in the source/drain of germanium nMOSFET. With adopting of the Implantation After Germanide (IAG) technique, P and Sb co-implantation technique and Multiple Implantation and Multiple Annealing (MIMA) technique, the electron Schottky barrier height of NiGe/Ge contact is modulated to 0.1eV, the thermal stability of NiGe is improved to 600°C and the contact resistivity of metal/n-Ge contact is drastically reduced to 3.8×10−7Ω•cm2, respectively. Besides, a reduced source/drain parasitic resistance is demonstrated in the fabricated Ge nMOSFET. Readers will find useful information about the source/drain engineering technique for high-performance CMOS devices at future technology node.

Download or read book A Study of MOS Capacitors and MOSFETs Using Erbium Oxide as the Gate Dielectric written by Gary A. Pickrell and published by . This book was released on 1992 with total page 210 pages. Available in PDF, EPUB and Kindle. Book excerpt:

Download or read book Investigation of Different Dielectric Materials as Gate Insulator for MOSFET written by Ritika R. Oswal and published by . This book was released on 2014 with total page 69 pages. Available in PDF, EPUB and Kindle. Book excerpt: The scaling of semiconductor transistors has led to a decrease in thickness of the silicon dioxide layer used as gate dielectric. The thickness of the silicon dioxide layer is reduced to increase the gate capacitance, thus increasing the drain current. If the thickness of the gate dielectric decreases below 2nm, the leakage current due to the tunneling increases drastically. Hence it is necessary to replace the gate dielectric, silicon dioxide, with a physically thicker oxide layer of high-k materials like Hafnium oxide and Titanium oxide. High-k dielectric materials allow the capacitance to increase without a huge leakage current. Hafnium oxide and Titanium oxide films are deposited by reactive magnetron sputtering from Hafnium and Titanium targets respectively. These oxide layers are used to create metal-insulator-metal (MIM) structures using aluminum as the top and bottom electrodes. The films are deposited at various O2/Ar gas flow ratios, substrate temperatures, and process pressures. After attaining an exact recipe for these oxide layers that exhibit the desired parameters, MOS capacitors are fabricated with n-Si and p-Si substrates having aluminum electrodes at the top and bottom of each. Comparing the parameters of Hafnium oxide- and Titanium oxide- based MOS capacitors, MOSFET devices are designed with Hafnium oxide as gate dielectric.

Download or read book Interface and Stress Engineering in Germanium Metal oxide semiconductor Field effect transistors for High Performance Application written by Masaharu Kobayashi and published by . This book was released on 2009 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt: Germanium has been attracting great interests as a high mobility channel material for MOSFETs to replace silicon in LSI chips. Germanium also has advantages over any other high mobility material, such as high compatibility to Silicon LSI technologies, low temperature process which enable 3DIC integration with low thermal budget. In order to realize high performance Ge MOS integration in future technology nodes, device and process issues have to be thoroughly addressed and investigated. In this work, first, the property of metal/Ge contact was studied. Since Ge suffers from very strong Fermi-level pinning near its valence band, n-type metal/Ge contact causes high contact resistance whatever workfunction metal is used. New technique, which is insertion of ultrathin insulator between metal and Ge, was proposed and Fermi-level depinning was experimentally demonstrated. In the second part, radical oxidation was investigated for GeO2 growth for highly reliable interface gate dielectric in high-k/Ge gate stack. Although Ge does not have chemically stable native oxide unlike Si, GeO2 has been regarded as a promising interface gate dielectric with high-k dielectric capping. High density radical oxidation enables very low temperature oxidation and provides high quality GeO2 with low interface states. In the third part, the effects of stress in Ge NMOSFETs were studied. Stress engineering has been playing a key role in the current high performance Si LSI technologies and it can also enhance device performance of Ge MOSFETs. Mobility enhancement was experimentally achieved by applying uniaxial stress to Ge NMOSFETs and performance limit of Ge NMOSFET with uniaxial stress was also theoretically examined. It is clarified that stress engineering is effective in future technology nodes.

Download or read book 1 f Noise in Hafnium Based High k Gate Dielectric MOSFETs and a Review of Modeling written by Siva Prasad Devireddy and published by ProQuest. This book was released on 2007 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt: For next generation MOSFETs, the constant field scaling rule dictates a reduction in the gate oxide thickness among other parameters. Consequently, gate leakage current becomes a serious issue with very thin SiO2 that is conventionally used as gate dielectric since it is the native oxide for Si substrate. This has driven an industry wide search for suitable alternate 'high-k' gate dielectric that has a high value of relative permittivity compared to SiO2 thereby presenting a physically thicker barrier for tunneling carriers while providing a high gate capacitance. Consequently, it is essential to study the properties of these novel materials and the interfaces that they form with the substrate, gate or other dielectrics in a multi-level stack. The main focus of this work is the 1/f noise that is specifically used as a characterization tool to evaluate the performance of high-k MOSFETs. Nevertheless, DC and split C-V characterization are done as well to obtain device performance parameters that are used in the noise analysis. At first, the room temperature 1/f noise characteristics are presented for n- and p-channel poly-Si gated MOSFETs with three different gate dielectrics- HfO2, Al2O3 (top layer)/HfO2 (bottom layer), HfAlOx. The devices had either 1 nm or 4 nm SiO2 interfacial layer, thus presenting an opportunity to understand the effects of interfacial layer thickness on noise and carrier mobility. In the initial study, the analysis of noise is done based on the Unified Flicker Noise Model. Next, a comparative study of 1/f noise behavior is presented for TaSiN (NMOS) and TiN (PMOS) gated MOSFETs with HfO2 gate dielectric and their poly-Si gated counterparts. Additionally, in TaSiN MOSFETs, the effect of the different deposition methods employed for interfacial layer formation on the overall device performance is studied. Finally, the 'Multi-Stack Unified Noise' model (MSUN) is proposed to better model/characterize the 1/f noise in multi-layered high-k MOSFETs. This model takes the non-uniform trap density profile and other physical properties of the constituent gate dielectrics into account. The MSUN model is shown to be in excellent agreement with the experimental data obtained on TaSiN/HfO 2/SiO2 MOSFETs in the 78-350 K range. Additionally, the MSUN model is expressed in terms of surface potential based parameters for inclusion in to the circuit simulators.

Download or read book Atomic layer deposited High k Gate Oxides on Germanium written by Shankar Swaminathan and published by . This book was released on 2010 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt: Germanium (Ge) has emerged as a promising candidate for surface channels in highly-scaled field-effect-transistors (FETs), as performance and reliability issues are likely to limit the use of conventional Si-based complementary-metal-oxide-semiconductor (CMOS) transistors beyond the 15nm technology node. Lack of a high quality and stable thermal oxide of germanium has prompted interest in the use of high-k (high dielectric-constant) gate dielectrics on Ge channels. An interface passivation layer (IPL) between the high-k film and the Ge substrate appears to be necessary to avoid large defect densities characteristic of atomically-abrupt high-k (ZrO2 or HfO2)/Ge interfaces. Atomic layer deposition (ALD) is a useful high-k metal oxide film growth technique due to the precise nature of thickness control and uniformity of thickness for ultra-thin films. The use of ALD to synthesize deposited IPLs interposed between the Ge channel and an overlying high-k layer has not been studied extensively. For this research, a laboratory-scale ALD reactor was designed and built for Al2O3 and TiO2 chemistries with liquid metal organic precursors and H2O as oxidant. A novel in situ x-ray photoelectron spectroscopy (XPS) setup that uses a differentially pumped electrons lens and analyzer was incorporated successfully into the ALD growth chamber, enabling the real-time monitoring of chemical states in the ALD ambient. This system demonstrated collection of in situ spectra within 10's of seconds of an ALD precursor pulse, without moving the substrate or changing its temperature. Pre-ALD Ge surface functionalization by in situ oxidant dosing ("pre-pulsing") in the growth chamber was studied and optimized to synthesize a high-quality ALD-Al2O3/Ge interface, with a midgap density of interface states (Dit) ~ 2x1011 cm-2 eV-1. In situ XPS studies revealed the influence of hydroxyl ( -OH) termination of the Ge surface in passivating dangling bonds that lead to fast trapping. The evolution of Ge-O bonding states during pre-pulsing was correlated with the observed improvements in hysteresis, frequency dispersion of the gate capacitance, and the response of fast (band-edge) and slow (midgap) interface states. The effects of scaling the physical thickness of the ALD-Al2O3 down to the sub-nanometer regime on key electrical parameters such as Dit, capacitance density, leakage current density and fixed charge were studied. The ultra-thin ALD-Al2O3/Ge interface, unlike in Si, was observed to resist sub-cutaneous oxidation, evidencing the capacitance scaling potential of these IPLs. Photoemission studies done using synchrotron radiation suggested a possible mechanism for FGA-induced passivation of interface states and revealed excellent valence and conduction band offsets of ALD-Al2O3 to Ge (> 2.5eV). Thus, unlike oxide or oxynitride passivation, ALD-Al2O3 IPLs promise an effective leakage barrier to hole and electron injection in addition to providing low Dit. Aggressive gate capacitance scaling requirements for future CMOS technology necessitates the use of the so-called "higher-k" dielectrics such as TiO2 (k> 25) in the gate stack. However, the conduction band offset of the TiO2/Ge interface is very low (~ 0.2eV), resulting in unacceptably high gate leakage. To this end, successful integration of ultrathin (~ 1 nm), interface-engineered ALD-Al2O3 IPLs in ALD-TiO2 gate dielectric stacks on Ge was demonstrated through detailed physical and electrical characterization studies. These IPLs, owing to their large bandgap (~ 6.6eV), were observed to dramatically reduce the gate leakage at the TiO2/Ge interface by 6 orders of magnitude at the flatband voltage. The Platinum-gated bilayer devices exhibited excellent C-V characteristics down to a CET of 1.2nm and exhibited a minimum Dit ~ 3x1011 cm-2 eV-1 near midgap after FGA. Taking into account a typical 0.4nm contribution due to the quantum capacitance of the Ge substrate, these devices are well-suited to achieve the sub-nanometer scaling benchmarks for the 22nm node and beyond. Extensive temperature- and frequency-dependent defect characterization of the bilayer devices evidenced an unpinned oxide/semiconductor interface and showed that thermally-activated electron transport into shallow defect states in the TiO2 (~0.25eV below the CB edge) near the TiO2/Al2O3 interface resulted in a temperature-dependent dispersion of the accumulation capacitance density.

Download or read book Physical and Electrical Characterization of Zirconium Dioxide as a MOSFET Gate Insulator written by Noel Philip Hoilien and published by . This book was released on 2004 with total page 238 pages. Available in PDF, EPUB and Kindle. Book excerpt:

Download or read book CoNiSi2 Fully Silicided FUSI Metal Gate in MOS Capacitor and Its Characterization written by Jun Liu and published by . This book was released on 2004 with total page 114 pages. Available in PDF, EPUB and Kindle. Book excerpt: The Scaling of the device feature sizes has led the progress in MOS integrated circuit technology. In order to provide better performance and high packing density in the limited chip space , scaling down of the channel length of MOSFET becomes essential in ULSI fabrication technologies. The thinner gate oxide is required to reduce the short channel effects and maintain gate controllability over the channel with higher driver current capability. When dielectric (SiO2) thickness approaches near 1nm in CMOS devices scale, new materials such as high-k dielectrics and metal gate electrodes has been investigated in order to ensure continued scaling of the technology. Depletion layer at poly-Si/gate dielectric interface becomes significant. Poly-Si also has several problems such as boron penetration, and high gate resistance RC time delay. So those important issues lead to the use of alternative gate electrodes, such as metals. Eliminating poly-silicon depletion has the advantage of more scaling down without decreasing oxide thickness. Low sheet resistance using metal gates improves device performance especially in AC. Replacing poly-si requires two metals with compatible work function and tunable performance. The work function range required is 4.1~ 4.4eV for NMOS and 4.8~5.1eV for PMOS .Several metals as a metal gate electrode with different process techniques have been published. Many metals, metal nitrides, metal silicon nitrides and metal oxides were investigated for dual metal gate approach such as Ta, TaN, TaSiN, TiN, IrO2, RuO2. Tunable metal techniques using nitrogen implantaion is also reported. Those metals require special processes such as gate-last or lift-off to avoid difficult issues related to etching, high thermal budget and dual metal gate modification. Silicidation techniques have received much attention in salicide process to reduce contact resistivity on the source, drain and gate for several years. Recently several metal silicided gates, such as CoSi2 and NiSi, were demonstrated. NiSi has two different work functions with N+ and P+ poly-silicon, and CoSi2 has a mid-gap work function and better thermal stability than NiSi. So this work is to combine these two materials, and investigate the potential of CoNiSi2 as metal gate on MOS capacitors. It is found that both As and B influence the work function of the FUSI significantly. FUSI metal gate doesn't degrade the gate oxide quality, as indicated by identical oxide leakage, interface state density after FUSI. The importance of this work is to use different Co:Ni ratio in CoNiSi2 formation process, which proves Co:Ni ratio is an important factor to influence the As and B dopant piling up at the interface of metal gate and dielectric and then influence the work function of whole device

Download or read book Electrical Properties of Ge Metal oxide semiconductor Capacitors with High k La2O3 Gate Dielectric Incorporated by N Or and Ti Project Supported by the National Natural Science Foundation of China No 61274112 the Natural Science Foundation of Hubei Province No 2011CDB165 and the Scientific Research Program of Huanggang Normal University No 2012028803 written by and published by . This book was released on 2016 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt: Abstract: LaON, LaTiO and LaTiON films are deposited as gate dielectrics by incorporating N or/and Ti into La2 O3 using the sputtering method to fabricate Ge MOS capacitors, and the electrical properties of the devices are carefully examined. LaON/Ge capacitors exhibit the best interface quality, gate leakage property and device reliability, but a smaller k value (14.9). LaTiO/Ge capacitors exhibit a higher k value (22.7), but a deteriorated interface quality, gate leakage property and device reliability. LaTiON/Ge capacitors exhibit the highest k value (24.6), and a relatively better interface quality (3.1 × 10 11 eV −1 cm −2 ), gate leakage property (3.6 × 10 −3 A/cm 2 at V g = 1 V + V fb ) and device reliability. Therefore, LaTiON is more suitable for high performance Ge MOS devices as a gate dielectric than LaON and LaTiO materials.