Download or read book A Scalable New Cache Coherence Protocol for Hierarchical Distributed Shared Memory written by Phanindra K. Mannava and published by . This book was released on 1994 with total page 64 pages. Available in PDF, EPUB and Kindle. Book excerpt:

Download or read book Scalable Shared Memory Multiprocessing written by Daniel E. Lenoski and published by Elsevier. This book was released on 2014-06-28 with total page 364 pages. Available in PDF, EPUB and Kindle. Book excerpt: Dr. Lenoski and Dr. Weber have experience with leading-edge research and practical issues involved in implementing large-scale parallel systems. They were key contributors to the architecture and design of the DASH multiprocessor. Currently, they are involved with commercializing scalable shared-memory technology.

Download or read book SOFTWARE SHARED VIRTUAL MEMORY written by Chit-Ho Dominic Hung and published by Open Dissertation Press. This book was released on 2017-01-26 with total page 174 pages. Available in PDF, EPUB and Kindle. Book excerpt: This dissertation, "A Software Shared Virtual Memory System With Three Way Coherence Protocols on the Intel Single-chip Cloud Computer" by Chit-ho, Dominic, Hung, 熊哲皓, was obtained from The University of Hong Kong (Pokfulam, Hong Kong) and is being sold pursuant to Creative Commons: Attribution 3.0 Hong Kong License. The content of this dissertation has not been altered in any way. We have altered the formatting in order to facilitate the ease of printing and reading of the dissertation. All rights not granted by the above license are retained by the author. Abstract: With the advancement of design and fabrication of high-performance integrated circuits technology, it is foreseeable that processors with more than 1,000 cores per die will appear in the near future. However, these many-core architectures have introduced a lot of challenges at the memory system level, such as complicated cache coherence and limited memory access speed, to name a few. This thesis focuses on one prominent many-core prototype - the Intel's Single-chip Cloud Computer (SCC). The SCC architecture does not provide hardware cache coherency. Instead, it relies on on-chip programmable memory. The baseline coherence protocol for the SCC is the Software Managed Coherence (SMC) layer. To achieve memory consistency, it accesses shared memory without part of the typical cache hierarchy for efficient invalidation and flushing. We found that performance provided by this coherence layer in this manner is sub-optimal because accesses of shared memory would all turn into data update messages within the network mesh. As cache locality could not be exploited to its full potential, the execution pipelines stall much often for memory fetches from outside the chip. This research is to address the performance problem of shared virtual memory consistency for this cache in-coherent architecture. Oriented at sitting data on-chip as much as possible to reduce memory accesses external to the chip, we propose two techniques to leverage the cache hierarchy to full and reside data in the on-chip scratchpad memory. First, targeted at the architectural specificity of the hardware, we redesigned traditional software distributed shared memory (SDSM) to allow shared data be treated transparently like private memory so the cache hierarchy can be fully utilised without sacrificing memory consistency. Second, we propose a distance-aware page allocation scheme that samples access frequencies and select the most frequently-recently used pages to be stored on the on-chip scratchpad memory. Our experimental results show that our first technique, the ordinary SDSM outperforms the current SMC approach by 5 times. Moreover, in some cases, with the second technique that is based on scratchpad memory, our proposed system outperforms further by an additional 1.57 times. Our experiments also demonstrated that the SMC approach is not scalable due to congestion of the network mesh by coherence traffic generated while the two new approaches continued to scale well. The main contribution of this research is the implementation of a cache coherence software library system built for an architecture that comes with non-coherent cache hardware and just relies on software-defined cache. This new cache hierarchy has evidently opened the door for smarter and faster inter-processor-core data sharing without the need of complicated cache coherence hardware. Subjects: Distributed shared memory Cloud computing

Download or read book A Primer on Memory Consistency and Cache Coherence written by Daniel J. Sorin and published by Morgan & Claypool Publishers. This book was released on 2011 with total page 215 pages. Available in PDF, EPUB and Kindle. Book excerpt: Many modern computer systems and most multicore chips (chip multiprocessors) support shared memory in hardware. In a shared memory system, each of the processor cores may read and write to a single shared address space. For a shared memory machine, the memory consistency model defines the architecturally visible behavior of its memory system. Consistency definitions provide rules about loads and stores (or memory reads and writes) and how they act upon memory. As part of supporting a memory consistency model, many machines also provide cache coherence protocols that ensure that multiple cached copies of data are kept up-to-date. The goal of this primer is to provide readers with a basic understanding of consistency and coherence. This understanding includes both the issues that must be solved as well as a variety of solutions. We present both highlevel concepts as well as specific, concrete examples from real-world systems. Table of Contents: Preface / Introduction to Consistency and Coherence / Coherence Basics / Memory Consistency Motivation and Sequential Consistency / Total Store Order and the x86 Memory Model / Relaxed Memory Consistency / Coherence Protocols / Snooping Coherence Protocols / Directory Coherence Protocols / Advanced Topics in Coherence / Author Biographies

Download or read book The Performance and Scalability of Distributed Shared Memory Cache Coherence Protocols written by Mark Andrew Heinrich and published by . This book was released on 1998 with total page 358 pages. Available in PDF, EPUB and Kindle. Book excerpt:

Download or read book A Primer on Memory Consistency and Cache Coherence written by Daniel Sorin and published by Springer Nature. This book was released on 2011-05-10 with total page 206 pages. Available in PDF, EPUB and Kindle. Book excerpt: Many modern computer systems and most multicore chips (chip multiprocessors) support shared memory in hardware. In a shared memory system, each of the processor cores may read and write to a single shared address space. For a shared memory machine, the memory consistency model defines the architecturally visible behavior of its memory system. Consistency definitions provide rules about loads and stores (or memory reads and writes) and how they act upon memory. As part of supporting a memory consistency model, many machines also provide cache coherence protocols that ensure that multiple cached copies of data are kept up-to-date. The goal of this primer is to provide readers with a basic understanding of consistency and coherence. This understanding includes both the issues that must be solved as well as a variety of solutions. We present both highlevel concepts as well as specific, concrete examples from real-world systems. Table of Contents: Preface / Introduction to Consistency and Coherence / Coherence Basics / Memory Consistency Motivation and Sequential Consistency / Total Store Order and the x86 Memory Model / Relaxed Memory Consistency / Coherence Protocols / Snooping Coherence Protocols / Directory Coherence Protocols / Advanced Topics in Coherence / Author Biographies

Download or read book Multi Core Cache Hierarchies written by Rajeev Balasubramonian and published by Morgan & Claypool Publishers. This book was released on 2011-06-06 with total page 155 pages. Available in PDF, EPUB and Kindle. Book excerpt: A key determinant of overall system performance and power dissipation is the cache hierarchy since access to off-chip memory consumes many more cycles and energy than on-chip accesses. In addition, multi-core processors are expected to place ever higher bandwidth demands on the memory system. All these issues make it important to avoid off-chip memory access by improving the efficiency of the on-chip cache. Future multi-core processors will have many large cache banks connected by a network and shared by many cores. Hence, many important problems must be solved: cache resources must be allocated across many cores, data must be placed in cache banks that are near the accessing core, and the most important data must be identified for retention. Finally, difficulties in scaling existing technologies require adapting to and exploiting new technology constraints. The book attempts a synthesis of recent cache research that has focused on innovations for multi-core processors. It is an excellent starting point for early-stage graduate students, researchers, and practitioners who wish to understand the landscape of recent cache research. The book is suitable as a reference for advanced computer architecture classes as well as for experienced researchers and VLSI engineers. Table of Contents: Basic Elements of Large Cache Design / Organizing Data in CMP Last Level Caches / Policies Impacting Cache Hit Rates / Interconnection Networks within Large Caches / Technology / Concluding Remarks

Download or read book A Scalable Hierarchical Cache Coherence Protocol written by Deborah Anne Wallach and published by . This book was released on 1990 with total page 98 pages. Available in PDF, EPUB and Kindle. Book excerpt:

Download or read book Distributed Shared Memory written by Jelica Protic and published by John Wiley & Sons. This book was released on 1997-08-10 with total page 384 pages. Available in PDF, EPUB and Kindle. Book excerpt: The papers present in this text survey both distributed shared memory (DSM) efforts and commercial DSM systems. The book discusses relevant issues that make the concept of DSM one of the most attractive approaches for building large-scale, high-performance multiprocessor systems. The authors provide a general introduction to the DSM field as well as a broad survey of the basic DSM concepts, mechanisms, design issues, and systems. The book concentrates on basic DSM algorithms, their enhancements, and their performance evaluation. In addition, it details implementations that employ DSM solutions at the software and the hardware level. This guide is a research and development reference that provides state-of-the art information that will be useful to architects, designers, and programmers of DSM systems.

Download or read book A Primer on Memory Consistency and Cache Coherence written by Vijay Nagarajan and published by Morgan & Claypool Publishers. This book was released on 2020-02-04 with total page 296 pages. Available in PDF, EPUB and Kindle. Book excerpt: Many modern computer systems, including homogeneous and heterogeneous architectures, support shared memory in hardware. In a shared memory system, each of the processor cores may read and write to a single shared address space. For a shared memory machine, the memory consistency model defines the architecturally visible behavior of its memory system. Consistency definitions provide rules about loads and stores (or memory reads and writes) and how they act upon memory. As part of supporting a memory consistency model, many machines also provide cache coherence protocols that ensure that multiple cached copies of data are kept up-to-date. The goal of this primer is to provide readers with a basic understanding of consistency and coherence. This understanding includes both the issues that must be solved as well as a variety of solutions. We present both high-level concepts as well as specific, concrete examples from real-world systems. This second edition reflects a decade of advancements since the first edition and includes, among other more modest changes, two new chapters: one on consistency and coherence for non-CPU accelerators (with a focus on GPUs) and one that points to formal work and tools on consistency and coherence.

Download or read book Identification and Optimization of Sharing Patterns for Scalable Shared memory Multiprocessors written by Stefanos Kaxiras and published by . This book was released on 1998 with total page 516 pages. Available in PDF, EPUB and Kindle. Book excerpt:

Download or read book A Scalable Cache Coherence Protocol for a Hierarchical Bus based Multiprocessor written by Wuucheng Huang and published by . This book was released on 1990 with total page 180 pages. Available in PDF, EPUB and Kindle. Book excerpt:

Download or read book Development and Validation of a Hierarchical Memory Model Incorporating CPU and Memory Operation Overlap written by and published by . This book was released on 1997 with total page 21 pages. Available in PDF, EPUB and Kindle. Book excerpt: Distributed shared memory architectures (DSM's) such as the Origin 2000 are being implemented which extend the concept of single-processor cache hierarchies across an entire physically-distributed multiprocessor machine. The scalability of a DSM machine is inherently tied to memory hierarchy performance, including such issues as latency hiding techniques in the architecture, global cache-coherence protocols, memory consistency models and, of course, the inherent locality of reference in algorithms of interest. In this paper, we characterize application performance with a {open_quotes}memory-centric{close_quotes} view. Using a simple mean value analysis (MVA) strategy and empirical performance data, we infer the contribution of each level in the memory system to the application's overall cycles per instruction (cpi). We account for the overlap of processor execution with memory accesses - a key parameter which is not directly measurable on the Origin systems. We infer the separate contributions of three major architecture features in the memory subsystem of the Origin 2000: cache size, outstanding loads-under-miss, and memory latency.

Download or read book A suite of hierarchical cache coherence protocols written by Umakishore Ramachandran and published by . This book was released on 1988 with total page 26 pages. Available in PDF, EPUB and Kindle. Book excerpt:

Download or read book Update based Cache Coherence Protocols for Scalable Shared memory Multiprocessors written by Stanford University. Computer Systems Laboratory and published by . This book was released on 1993 with total page 26 pages. Available in PDF, EPUB and Kindle. Book excerpt: In this paper, two hardware-controlled update-based cache coherence protocols are presented. The paper discusses the two major disadvantages of the update protocols: inefficiency of updates and the mismatch between the granularity of synchronization and the data transfer. The paper presents two enhancements to the update-based protocols, a write combining scheme and a finer grain synchronization, to overcome these disadvantages. The results demonstrate the effectiveness of these enhancements that, when used together, allow the update-based protocols to significantly improve the execution time of a set of scientific applications when compared to three invalidate-based protocols.

Download or read book The Cache Coherence Problem in Shared Memory Multiprocessors written by Igor Tartalja and published by Wiley-IEEE Computer Society Press. This book was released on 1996-02-13 with total page 368 pages. Available in PDF, EPUB and Kindle. Book excerpt: The book illustrates state-of-the-art software solutions for cache coherence maintenance in shared-memory multiprocessors. It begins with a brief overview of the cache coherence problem and introduces software solutions to the problem. The text defines and details static and dynamic software schemes, techniques for modeling performance evaluation mechanisms, and performance evaluation studies.

Download or read book Scalable Caching Techniques for a Weakly Coherent Memory written by K. Zamanifar and published by . This book was released on 1995 with total page 16 pages. Available in PDF, EPUB and Kindle. Book excerpt: Abstract: "There is a growing acceptance that general purpose parallel computers need to be based on a scalable shared memory computational model, with the ability to exploit data locality for good performance. Today, this is commonly achieved by mapping the model onto a distributed memory computer with a scalable interconnect (supporting linear increases in bisection bandwidth). Example machines are the Cray T3D, IBM SP2 and Intel Paragon, which can scale in performance to 100's or 1000's of processors. This results in a two-level memory hierarchy, in which data is either local or shared across the machine. The next few years will see a trend in the move towards cache coherent multiprocessors, using the techniques employed by machines such as the KSR (cache-only memory) and the DASH (distributed directories). An example is the forthcoming Silicon Graphics cache coherent multiprocessor. This will simplify the programming model by presenting a single level memory hierarchy, consisting of a system-wide shared address space. Multiple copies of a shared variable are then automatically maintained in a coherent state by the machine. This paper describes a highly scalable caching technique, which is targeted at a specific form of shared memory model, called the WPRAM. Shared data is weakly coherent, in that a processor wishing to read newly written shared data must explicitly synchronise in some way with the writer of that data. The example provided supports coherency for barrier synchronisation operations, but can be extended to other forms. An example of the use of this method is shown through an implementation of the simplex method for linear programming. Results are based on a simulation of a scalable distributed memory machine. An analytical model is used to describe the performance of the algorithm and verify the simulation results."