Download or read book A CMOS Clock and Data Recovery Circuit for Giga bit s Serial Data Communications written by Hui Wang and published by . This book was released on 1998 with total page 298 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book CMOS Multichannel Single Chip Receivers for Multi Gigabit Optical Data Communications written by Paul Muller and published by Springer Science & Business Media. This book was released on 2007-10-29 with total page 207 pages. Available in PDF, EPUB and Kindle. Book excerpt: In the world of optical data communications this book will be an absolute must-read. It focuses on optical communications for short and very short distance applications and discusses the monolithic integration of optical receivers with processing elements in standard CMOS technologies. What’s more, it provides the reader with the necessary background knowledge to fully understand the trade-offs in short-distance communication receiver design and presents the key issues to be addressed in the development of such receivers in CMOS technologies. Moreover, novel design approaches are presented.
Download or read book Low Power Clock and Data Recovery Integrated Circuits written by Shahab Ardalan and published by . This book was released on 2007 with total page 121 pages. Available in PDF, EPUB and Kindle. Book excerpt: Advances in technology and the introduction of high speed processors have increased the demand for fast, compact and commercial methods for transferring large amounts of data. The next generation of the communication access network will use optical fiber as a media for data transmission to the subscriber. In optical data or chip-to-chip data communication, the continuous received data needs to be converted to discrete data. For the conversion, a synchronous clock and data are required. A clock and data recovery (CDR) circuit recovers the phase information from the data and generates the in-phase clock and data. In this dissertation, two clock and data recovery circuits for Giga-bits per second (Gbps) serial data communication are designed and fabricated in 180nm and 90nm CMOS technology. The primary objective was to reduce the circuit power dissipation for multi-channel data communication applications. The power saving is achieved using low swing voltage signaling scheme. Furthermore, a novel low input swing Alexander phase detector is introduced. The proposed phase detector reduces the power consumption at the transmitter and receiver blocks. The circuit demonstrates a low power dissipation of 340[mu]W/Gbps in 90nm CMOS technology. The CDR is able to recover the input signal swing of 35mVp. The peak-to-peak jitter is 21ps and RMS jitter is 2.5ps. Total core area excluding pads is approximately 0.01mm2.
Download or read book CMOS Current Mode Circuits for Data Communications written by Fei Yuan and published by Springer Science & Business Media. This book was released on 2007-04-26 with total page 306 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book deals with the analysis and design of CMOS current-mode circuits for data communications. CMOS current-mode sampled-data networks, i.e. switched-current circuits, are excluded. Major subjects covered in the book include: a critical comparison of voltage-mode and current-mode circuits; the building blocks of current-mode circuits: design techniques; modeling of wire channels, electrical signaling for Gbps data communications; ESD protection for current-mode circuits and more. This book will appeal to IC design engineers, hardware system engineers and others.
Download or read book CMOS Circuits for High Speed Serial Data Communication written by Xiaoyu Xi and published by . This book was released on 1997 with total page 132 pages. Available in PDF, EPUB and Kindle. Book excerpt: At the receiver end, a clock recovery circuit based on a charge pump phase locked loop is proposed. The VCO has an internal feedback loop to adjust the duty cycle at different frequency. A simple conventional phase detector with a limited output swing is used to achieve the high working frequency. A modified symmetrical charge pump circuit improves linearity of the output current versus the input UP and DOWN signal. Some characteristics such as impulse capture range and lock range are estimated from the simulations. All the designs assume 0.5um single-poly triple-metal CMOS technology. This work presents an analysis to the system as well as individual parts and explores the possibility of CMOS solutions for gigabit data communication. It could be used or adopted in future designs in similar applications.
Download or read book A 10 Gb s CMOS Clock and Data Recovery Circuit written by Jafar Savoj and published by . This book was released on 2001 with total page 238 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Design of Clock Data Recovery Integrated Circuit for High Speed Data Communication Systems written by Jinghua Li and published by . This book was released on 2010 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt: Demand for low cost Serializer and De-serializer (SerDes) integrated circuits has increased due to the widespread use of Synchronous Optical Network (SONET)/Gigabit Ethernet network and chip-to-chip interfaces such as PCI-Express (PCIe), Serial ATA(SATA) and Fibre channel standard applications. Among all these applications, clock data recovery (CDR) is one of the key design components. With the increasing demand for higher bandwidth and high integration. Complementary metal-oxidesemiconductor (CMOS) implementation is now a design trend for the predominant products in this research work, a fully integrated 10Gb/s (OC-192) CDR architecture in standard 0.18 um CMOS is developed. The proposed architecture integrates the typically large off-chip filter capacitor by using two feed-forward paths configuration to generate the required zero and poles and satisfies SONET jitter requirements with a total power dissipation (including the buffers) of 290mW. The chip exceeds SONET OC-192 jitter tolerance mask, and high frequency jitter tolerance is over 0.31 UIpp by applying PRBS data with a pattern length of 231-1. The implementation is the first fully integrated 10Gb/s CDR IC which meets/exceeds the SONET standard in the literature. The second proposed CDR architecture includes an adaptive bang-bang control algorithm. For 6MHz sinusoidal jitter modulation, the new architecture reduces the tracking error to 11.4ps peak-to-peak, versus that of 19.7ps of the conventional bangbang CDR. The main contribution of the proposed architecture is that it optimizes the loop dynamics by adjusting the bang-bang bandwidth adaptively to minimize the steady state jitter of the CDR, which leads to an improved jitter tolerance performance. According to simulation, the jitter performance is improved by more than 0.04UI, which alleviates the stringent 0.1UI peak to peak jitter requirements in the PCIe/Fibre channel/Sonet Standard.
Download or read book Clock and Data Recovery Circuits for 10 Giga bit per second Broadband Receivers in 0 18 mu m CMOS written by Xinyu Chen and published by . This book was released on 2007 with total page 158 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Design and Modeling of Clock and Data Recovery Integrated Circuit in 130 Nm CMOS Technology for 10 Gb written by Maher Assaad and published by . This book was released on 2009 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt: Abstract This thesis describes the design and implementation of a fully monolithic 10 Gb/s phase and frequency-locked loop based clock and data recovery (PFLL-CDR) integrated circuit, as well as the Verilog-A modeling of an asynchronous serial link based chip to chip communication system incorporating the proposed concept. The proposed design was implemented and fabricated using the 130 nm CMOS technology offered by UMC (United Microelectronics Corporation). Different PLL-based CDR circuits topologies were investigated in terms of architecture and speed. Based on the investigation, we proposed a new concept of quarter-rate (i.e. the clocking speed in the circuit is 2.5 GHz for 10 Gb/s data rate) and dual-loop topology which consists of phase-locked and frequency-locked loop. The frequency-locked loop (FLL) operates independently from the phase-locked loop (PLL), and has a highly-desired feature that once the proper frequency has been acquired, the FLL is automatically disabled and the PLL will take over to adjust the clock edges approximately in the middle of the incoming data bits for proper sampling. Another important feature of the proposed quarter-rate concept is the inherent 1-to-4 demultiplexing of the input serial data stream. A new quarter-rate phase detector based on the non-linear early-late phase detector concept has been used to achieve the multi-Giga bit/s speed and to eliminate the need of the front-end data pre-processing (edge detecting) units usually associated with the conventional CDR circuits. An eight-stage differential ring oscillator running at 2.5 GHz frequency center was used for the voltage-controlled oscillator (VCO) to generate low-jitter multi-phase clock signals. The transistor level simulation results demonstrated excellent performances in term of locking speed and power consumption. In order to verify the accuracy of the proposed quarter-rate concept, a clockless asynchronous serial link incorporating the proposed concept and communicating two chips at 10 Gb/s has been modelled at gate level using the Verilog-A language and time-domain simulated.
Download or read book Circuits at the Nanoscale written by Krzysztof Iniewski and published by CRC Press. This book was released on 2018-10-08 with total page 602 pages. Available in PDF, EPUB and Kindle. Book excerpt: Circuits for Emerging Technologies Beyond CMOS New exciting opportunities are abounding in the field of body area networks, wireless communications, data networking, and optical imaging. In response to these developments, top-notch international experts in industry and academia present Circuits at the Nanoscale: Communications, Imaging, and Sensing. This volume, unique in both its scope and its focus, addresses the state-of-the-art in integrated circuit design in the context of emerging systems. A must for anyone serious about circuit design for future technologies, this book discusses emerging materials that can take system performance beyond standard CMOS. These include Silicon on Insulator (SOI), Silicon Germanium (SiGe), and Indium Phosphide (InP). Three-dimensional CMOS integration and co-integration with Microelectromechanical (MEMS) technology and radiation sensors are described as well. Topics in the book are divided into comprehensive sections on emerging design techniques, mixed-signal CMOS circuits, circuits for communications, and circuits for imaging and sensing. Dr. Krzysztof Iniewski is a director at CMOS Emerging Technologies, Inc., a consulting company in Vancouver, British Columbia. His current research interests are in VLSI ciruits for medical applications. He has published over 100 research papers in international journals and conferences, and he holds 18 international patents granted in the United States, Canada, France, Germany, and Japan. In this volume, he has assembled the contributions of over 60 world-reknown experts who are at the top of their field in the world of circuit design, advancing the bank of knowledge for all who work in this exciting and burgeoning area.
Download or read book Silicon Germanium written by Raminderpal Singh and published by John Wiley & Sons. This book was released on 2004-03-15 with total page 368 pages. Available in PDF, EPUB and Kindle. Book excerpt: "An excellent introduction to the SiGe BiCMOS technology, from the underlying device physics to current applications." -Ron Wilson, EETimes "SiGe technology has demonstrated the ability to provide excellent high-performance characteristics with very low noise, at high power gain, and with excellent linearity. This book is a comprehensive review of the technology and of the design methods that go with it." -Alberto Sangiovanni-Vincentelli Professor, University of California, Berkeley Cofounder, Chief Technology Officer, Member of Board Cadence Design Systems Inc. Filled with in-depth insights and expert advice, Silicon Germanium covers all the key aspects of this technology and its applications. Beginning with a brief introduction to and historical perspective of IBM's SiGe technology, this comprehensive guide quickly moves on to: * Detail many of IBM's SiGe technology development programs * Explore IBM's approach to device modeling and characterization-including predictive TCAD modeling * Discuss IBM's design automation and signal integrity knowledge and implementation methodologies * Illustrate design applications in a variety of IBM's SiGe technologies * Highlight details of highly integrated SiGe BiCMOS system-on-chip (SOC) design Written for RF/analog and mixed-signal designers, CAD designers, semiconductor students, and foundry process engineers worldwide, Silicon Germanium provides detailed insight into the modeling and design automation requirements for leading-edge RF/analog and mixed-signal products, and illustrates in-depth applications that can be implemented using IBM's advanced SiGe process technologies and design kits. "This volume provides an excellent introduction to the SiGe BiCMOS technology, from the underlying device physics to current applications. But just as important is the window the text provides into the infrastructure-the process development, device modeling, and tool development." -Ron Wilson Silicon Engineering Editor, EETimes "This book chronicles the development of SiGe in detail, provides an in-depth look at the modeling and design automation requirements for making advanced applications using SiGe possible, and illustrates such applications as implemented using IBM's process technologies and design methods." -John Kelly Senior Vice President and Group Executive, Technology Group, IBM
Download or read book Analog Circuit Design written by Michiel Steyaert and published by Springer Science & Business Media. This book was released on 2008-09-19 with total page 361 pages. Available in PDF, EPUB and Kindle. Book excerpt: Analog Circuit Design contains the contribution of 18 tutorials of the 17th workshop on Advances in Analog Circuit Design. Each part discusses a specific to-date topic on new and valuable design ideas in the area of analog circuit design. Each part is presented by six experts in that field and state of the art information is shared and overviewed. This book is number 17 in this successful series of Analog Circuit Design.
Download or read book Monolithic Phase Locked Loops and Clock Recovery Circuits written by Behzad Razavi and published by John Wiley & Sons. This book was released on 1996-04-18 with total page 516 pages. Available in PDF, EPUB and Kindle. Book excerpt: Featuring an extensive 40 page tutorial introduction, this carefully compiled anthology of 65 of the most important papers on phase-locked loops and clock recovery circuits brings you comprehensive coverage of the field-all in one self-contained volume. You'll gain an understanding of the analysis, design, simulation, and implementation of phase-locked loops and clock recovery circuits in CMOS and bipolar technologies along with valuable insights into the issues and trade-offs associated with phase locked systems for high speed, low power, and low noise.
Download or read book Clock and Data Recovery Circuit and Clock Synthesizers for 40 Gb s High density Serial I O links in 90 nm CMOS written by Georg Paul Emil von Bueren and published by . This book was released on 2011 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book CMOS Continuous Time Adaptive Equalizers for High Speed Serial Links written by Cecilia Gimeno Gasca and published by Springer. This book was released on 2014-09-22 with total page 164 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book introduces readers to the design of adaptive equalization solutions integrated in standard CMOS technology for high-speed serial links. Since continuous-time equalizers offer various advantages as an alternative to discrete-time equalizers at multi-gigabit rates, this book provides a detailed description of continuous-time adaptive equalizers design - both at transistor and system levels-, their main characteristics and performances. The authors begin with a complete review and analysis of the state of the art of equalizers for wireline applications, describing why they are necessary, their types, and their main applications. Next, theoretical fundamentals of continuous-time adaptive equalizers are explored. Then, new structures are proposed to implement the different building blocks of the adaptive equalizer: line equalizer, loop-filters, power comparator, etc. The authors demonstrate the design of a complete low-power, low-voltage, high-speed, continuous-time adaptive equalizer. Finally, a cost-effective CMOS receiver which includes the proposed continuous-time adaptive equalizer is designed for 1.25 Gb/s optical communications through 50-m length, 1-mm diameter plastic optical fiber (POF).
Download or read book Low Jitter Gb s CMOS Clock and Data Recovery Circuits for Large Synchronous Networks written by Sitt Tontisirin and published by . This book was released on 2008 with total page 0 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book CMOS Data Converters for Communications written by Mikael Gustavsson and published by Springer Science & Business Media. This book was released on 2005-12-15 with total page 394 pages. Available in PDF, EPUB and Kindle. Book excerpt: CMOS Data Converters for Communications distinguishes itself from other data converter books by emphasizing system-related aspects of the design and frequency-domain measures. It explains in detail how to derive data converter requirements for a given communication system (baseband, passband, and multi-carrier systems). The authors also review CMOS data converter architectures and discuss their suitability for communications. The rest of the book is dedicated to high-performance CMOS data converter architecture and circuit design. Pipelined ADCs, parallel ADCs with an improved passive sampling technique, and oversampling ADCs are the focus for ADC architectures, while current-steering DAC modeling and implementation are the focus for DAC architectures. The principles of the switched-current and the switched-capacitor techniques are reviewed and their applications to crucial functional blocks such as multiplying DACs and integrators are detailed. The book outlines the design of the basic building blocks such as operational amplifiers, comparators, and reference generators with emphasis on the practical aspects. To operate analog circuits at a reduced supply voltage, special circuit techniques are needed. Low-voltage techniques are also discussed in this book. CMOS Data Converters for Communications can be used as a reference book by analog circuit designers to understand the data converter requirements for communication applications. It can also be used by telecommunication system designers to understand the difficulties of certain performance requirements on data converters. It is also an excellent resource to prepare analog students for the new challenges ahead.
